Distributed Decoding in Cooperative Communications

In this paper, we present a novel relaying strategy called distributed and partial decoding. This strategy can be viewed as a variation of the decode and forward with the difference that the relay partially decodes the signal, re-transmits it to the destination, and the destination continues the decoding. By distributing the decoding process between the relay and the destination, the relay uses less processing power and less time. This is very suitable for practical applications in which relays are battery-operated (such as handsets) and do not want to use all their battery power on relaying the data of other users.Nokia CorporationNational Science Foundatio

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multirate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between 1/4 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.NokiaNational Science Foundatio

HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS

This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is describe

High-throughput multi-rate LDPC decoder based on architecture-oriented parity check matrices

Publication in the conference proceedings of EUSIPCO, Florence, Italy, 200

Configurable LDPC Decoder Architecture for Regular and Irregular Codes

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.NokiaNational Science Foundatio

Semi-Parallel Architectures For Real-time LDPC Coding

Masters ThesisError correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area-time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3,6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.NokiaNokia/Texas InstrumentsNational Instrument

Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding

This paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to SumProduct algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of ### ## LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of #### bits can achieve data rates up to ### Mbps

Semi-parallel architectures for real-time LDPC coding

Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. Low Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3, 6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes

Distributed partial decoding in cooperative communication systems

Increasing demand for wireless services is putting major pressure on network resources, which demands a new paradigm with a more efficient design. Recently, cooperative communications has emerged as a viable option for future wireless devices. Major improvements have been made in the theoretical analysis of cooperative communications and relay channels in recent years. But, most of the analyses have some simplifying assumptions that may not be valid in practice. These assumptions include using infinite-length block codes, zero processing delay, etc. This thesis considers cooperative communications from a practical point of view and identifies the benefits of cooperation when some of the theoretical assumptions are relaxed or changed. Several techniques are introduced to reduce the complexity of the system with minimal performance loss. We set up a framework for system design and show adaptability of our techniques to different scenarios. Our main focus is on the decode-and-forward relaying strategy with low density parity check (LDPC) codes. The thesis contributions in the field of cooperative communications fall into two main categories: algorithms and architectures. First, we focus on the complexity reduction in the algorithms and propose 'distributed partial decoding'. We demonstrate the benefits of partially decoding the codeword at the relay and distributing the decoding load between the relay and the destination. This results in major savings in terms of processing power and time at the relay with a very small loss in system performance. The architectural complexity and overhead of this scheme is much smaller than the original decode and forward strategy. The second contribution of this thesis is the design and implementation of a flexible LDPC decoder architecture that supports a family of LDPC with a variety of code rates and block lengths. This architecture is very suitable for cooperative environments where the cooperating pair and channel conditions and hence the code parameters are not known in advance. The third contribution relates to leveraging puncturing in cooperation. This work is the first to analyze cooperative communication with punctured LDPC codes. We propose structured puncturing patterns for quasi-cyclic LDPC codes and analyze the tradeoffs in designing good puncturing patterns for cooperative environments

Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding

Conference PaperThis paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3,6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.NokiaNokia/Texas InstrumentsNational Instrument